Hardware Acceleration

Validity and Zero Knowledge rollups add significant overheads to processing transactions and smart contracts. These costs are incurred in on-chain as well as off-chain activities. On-chain activities include publishing/data storage and verification while off-chain costs include computation, hardware infrastructure, and network management.

We have created a compiler on RISC-V instructions and wish to improve it further to reduce program lengths. Our zkEVM Soma relies entirely on lookup operations and draws inspiration from the Lasso/Jolt Paradigm. It consists of four key components: a) Committing to the witness (MSME over BN 254), b) Verifying Memory Consistency, c) Validating Operations through Lookups, and d) Ensuring the validity of indexes in Lookups through constraints. We have extensively benchmarked our first version of the VM, and our simulations have revealed performance bottlenecks primarily in the MSME commitment stage, followed by memory checks and lookup operations. Our initial strategy for hardware acceleration involves running MSME on FPGA followed by a more refined approach where we can perform Field operations on FPGA.

While the overall system remains in active development, we have identified certain fundamental operations (listed above) that will presumably not change and will remain bottlenecks. Therefore, we’ve finalized the system requirements for the first implementation. We have also selected two FPGA models that seem to fit the requirements. We have already made progress on the design analysis for the implementation on FPGA. We’ve largely fixed inputs and outputs. Our team is trying to work out the frequencies of both and finalize what devices the FPGA connects to and how often. Below is a list of activities we have planned in this direction and updates regarding their completion:

Particulars	Status
Lasso and Jolt Implementation	Done
Custom Complier Dev Risc	Done
Custom Compiler Dev RiscV with a reduced ISA	In-progress
Defining System Requirements	Done
Allocating functionality to the FPGA	In-progress
Identifying FPGA features	Done
Implementing FPGA design(HDL,RTL)	Not Started
Testing	Not Started
ASIC Development	Not Started